A power supply unit converts main AC voltage to one or more regulated DC voltages supplied to one or more loads, such as the internal components of a computer, server, or other electrical device.
FIG. 1 illustrates a conventional power supply unit under digital control for supplying power to a server. The power supply unit includes a primary side for power factor correction (PFC) and AC-to-DC voltage conversion, and a secondary side for DC-to-DC voltage conversion. The primary side receives an AC input voltage, such as the main line AC voltage, and outputs a DC bus voltage, such as 400V. The secondary side converts the DC bus voltage output from the primary side to a desired DC voltage level that is used by a coupled load, such as 15V, 5V, or 3.3V. The PFC stage on the primary side is digitally controlled by a first digital signal controller (DSC). The DC-to-DC stage on the secondary side is digitally controlled by a second DSC or an analog control chip with a microcontroller (MCU) for management. There is bi-directional or unidirectional communication signals sent between the primary side and the secondary side. One such communication signal is a Power Failure Warning (PFW) signal sent from the primary side to the secondary side. The PFW signal is used for notifying the secondary side of the power supply, and even systems coupled to the secondary side, that action needs to be taken due to the near term power supply shutoff, which is typically a few milliseconds after input AC voltage loss. This warning gives the secondary side and/or system an opportunity to take proper measures such as unloading so as to avoid any damage or failure or even operating data loss due to AC voltage loss. The PFW signal is triggered when the DC bus voltage output from the PFC stage has decreased to a threshold level, typically resulting from the loss of the input AC voltage. In an exemplary implementation, the PFC stage includes a bulk capacitor coupled to store energy and also smooth the ripple on the bus voltage. It is the bulk capacitor that provides the stored energy to the secondary side for continuous operation during the intervals between input AC voltage loss and device shutoff. In normal operation, the normal bus voltage is a function of the AC voltage. However, when there is a power failure, the AC voltage is lost, and the bus voltage output from the PFC stage goes down due to the discharging of the bulk capacitor. Because the dropping voltage may impact safe operation of the secondary side, in practice the DC bus voltage level needs to be monitored. If the monitored DC bus voltage drops to a PFW voltage threshold, then the PFW signal is sent from the primary side to the secondary side. If the DC bus voltage level subsequently drops further to a shutoff voltage threshold, then the power supply unit is shutoff, thereby shutting off power supplied to a coupled load.
FIG. 2 illustrates an exemplary timing diagram for implementation of the PFW signal relative to the bus voltage output from the PFC stage of FIG. 1. As shown in FIG. 2, the normal bus voltage is mainly a DC voltage plus secondary harmonics which depend on the characteristics of the specific power supply unit. At time t0, the input AC voltage is lost, at which point the DC bus voltage is no longer a function of the input AC voltage but instead is a result of the discharging energy stored in the bulk capacitor. The rate at which the bulk capacitor discharges, and therefore the rate at which the DC bus voltage decreases upon AC voltage loss is a function of the load coupled to the output of the DC-to-DC stage. The heavier the load, the greater the rate of DC bus voltage decrease. The rate at which the bus voltage decreases is barely changed if DC load has no change before and after AC voltage loss. When the DC bus voltage value decreases to a PFW voltage threshold, at time t1, the PFW signal is sent from the primary side to the secondary side. When the DC bus voltage value decreases to a shutoff voltage threshold, at time t2, the power supply unit is powered off. The time interval to is the time between issuing the PFW signal and power shutoff. The time interval tH is the hold-up time and is the time between input AC voltage loss and power shutoff. The hold-up time tH is the time delay before device shutoff provided by the bulk capacitor.
Conventionally, the PFW voltage threshold and the shutoff voltage threshold are fixed values. Generation of the PFW signal only relies on the set value for the PFW voltage threshold regardless of load condition. FIG. 3 illustrates exemplary timing diagrams corresponding to light load, intermediate load and heavy load conditions coupled to the power supply unit of FIG. 1. The timing diagram A corresponds to a heavy load condition. The timing diagram B corresponds to intermediate load conditions. The timing diagram C corresponds to light load conditions. As previously described and shown in FIG. 3, the rate of DC bus voltage decrease is greatest for heavy load conditions and least for light load conditions. Heavy loads draw more current which leads to faster drain of the energy stored in the bulk capacitor. Accordingly, the hold-up time tHA for heavy load conditions is shorter than the hold-up time tHB for intermediate load conditions, and the hold-up time tHB for intermediate load conditions is shorter than the hold-up time tHC for light load conditions. Similarly, the interval time between issuing the PFW signal and power shutoff is shortest for heavy load conditions, interval tA, longer for intermediate load conditions, interval tB, and longest for light load conditions, interval tC.
The PFW voltage threshold and the shutoff voltage threshold are set such that the time interval between issuance of the PFW signal and power shutoff is set for worst case load conditions so as to ensure proper shutoff in the case of power loss. As heavy load conditions result in the greatest rate of DC bus voltage decrease, the PFW voltage threshold value and therefore the time interval between the issuance of the PFW signal and power shutoff is set according to the minimum time needed for shutdown, which corresponds to the heavy load condition and interval tA. For light and intermediate load conditions, the rate of DC bus voltage decrease is not as great, but the PFW voltage threshold is set according to the heavy load condition. This results in premature issuance of the PFW signal for intermediate and light load conditions, which unnecessarily constrains the run time of the power supply unit. For example, the time interval between issuance of the PFW signal and power shutoff for intermediate load conditions, interval tB, is greater than the necessary amount of time, which is interval tA. This difference between interval tB and interval tA is time that the device could be running, but is not. Similarly, the time interval tC for light load conditions is also greater than the necessary interval tA, and again results in unnecessary device down time.